[llvm-dev] [GlobalISel] A Proposal for global instruction selection

[David Chisnall via llvm-dev]

On 19 Nov 2015, at 18:07, Quentin Colombet <qcolombet at apple.com> wrote:
> 
> 
>> On Nov 19, 2015, at 9:50 AM, David Chisnall <David.Chisnall at cl.cam.ac.uk> wrote:
>> 
>> On 19 Nov 2015, at 17:49, Quentin Colombet <qcolombet at apple.com> wrote:
>>> 
>>> I must miss something, but I don’t get what is the problem of lower the pointer to actual integer.
>> 
>> Pointers, in our architecture, are not integers.
> 
> Thanks for the clarifications.
> 
> So what you’re saying is that a inttoptr instruction is not a no-op on your architecture, is that right?

Correct.

> Or it can be a no-op only if the consumer of the pointer values can be done on the pointer register bank?

Yes (in some compilation models, we support 64-bit integers as pointers and 256-bit / 128-bit fat pointers, with the integer values being implicitly checked against a large region identified by one of the fat pointer registers, giving a coarse-grained sandbox that can communicate with the outside world via bounded pointers).

We currently have entirely separate fat pointer and integer register banks, though we’re investigating a mode where we’ll overlay the two on the same register file (though they’ll likely treat some things as sub-registers.

It also means that address space casts are not a no-op for us, which I believe is something that we share with some GPU ISAs (e.g. a 32-bit [or 16-bit] local pointer cast to a 64-bit global address space is not a simple sign/zero extension and so must be handled differently to an i32 -> i64 translation)

> Don’t know if that helps, but note that the registers are not typed, they just have size. The operations are typed.

That’s fine, once you’ve assigned values to register banks.  The issue is ensuring that we’re not throwing away the information that we need to do that assignment in the translation from LLVM IR to the new machine IR (i.e. which values are pointers, and which address space they are in).

> I am trying to understand the constraint to see how that would fit in the framework. That being said, anything that you could do in SDag should be possible as well in the new framework.

We currently add several new nodes to SDag: INTTOPTR, PTRTOINT, and PTRADD, and a new iFATPTR MVT.  The last is somewhat problematic, as we really want to have iFATPTR128 and iFATPTR256 (and, potentially, iFATPTR64 for an IoT/embedded variant).

David