[llvm-dev] Way to specify instruction latency in itinerary scheduling model

[Rail Shafigulin via llvm-dev]

>
> I suspect this is because you're specifying the pipeline structure but not
> the latencies. For example:
>
>   InstrItinData<IIC_FPDivD,      [InstrStage<1, [A2_FU]>],
>                                  [72, 0, 0]>,
>
> The '[InstrStage<1, [A2_FU]>]' specifies the pipeline structure (or, here,
> the first stage of the pipeline), and the '[72, 0, 0]' specifies the
> operand latencies (output on cycle 72, reads on cycle 0).
>
>  -Hal
>
> --
> Hal Finkel
> Assistant Computational Scientist
> Leadership Computing Facility
> Argonne National Laboratory
>


I see. Thank you.
-- 
R
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