[llvm-dev] [AArch64] Address computation folding

[Meador Inge via llvm-dev]

Hi,

I was looking at some AArch64 benchmarks and noticed some simple cases
where addresses are being folded into the address mode computations
and was curious as to why.  In particular, consider the following
simple example:

  void f2(unsigned long *x, unsigned long c)
  {
    x[c] *= 2;
  }

This generates:

  lsl x8, x1, #3
  ldr x9, [x0, x8]
  lsl x9, x9, #1
  str x9, [x0, x8]

Given the two uses of the address computation I was expecting this:

  add x8, x0, x1, lsl #3
  ldr x9, [x8]
  lsl x9, x9, #1
  str x9, [x8]

>From reading 'SelectAddrModeXRO' the computation is getting folded if
the add node is *only* used with memory related operations?

Why wouldn't it consider the number of uses in any operation?  The
"expected" code is easy to get by checking the number of uses.  This
may be desirable on some micro-architectures depending on the cost of
the various loads and stores.

-- Meador