[LLVMdev] Sub-Register extraction

[Romaric Jodin]

Hi everyone,

I'm working on a architecture where 2 32-bits registers can be use as one 64-bits register for some instructions.
We have some SIMD instructions with those registers.

I have a pattern to transform the "extractelt" node into a "EXTRACT_SUBREG" node.
My problem is that when LLVM is trying to get the high sub-register of a vector, it's doing a shift by 32 and then copy the low 32 bits sub-register. While it could just have copy the high 32 bits sub-register directly.

I found that the "EXTRACT_SUBREG" node is lowered into a "COPY" node. But I cannot manage to find where this node is lower into a shift + a copy.

Thank you all in advance,
Romaric