[LLVMdev] Problems with instruction scheduling

[Paweł Bylica]

Any comments?

On Thu, May 21, 2015 at 4:05 PM Paweł Bylica <chfast at gmail.com> wrote:

> Hi,
>
> I'm trying to fix PR23405 <https://llvm.org/bugs/show_bug.cgi?id=23405> -
> assert failure during instruction scheduling in llc. I have related but
> more generic questions.
>
> Is there any higher level description of the algorithm used for
> instruction scheduling in this case? It is new area for me and I would love
> to see bigger picture.
>
> My currently smallest test case contains 90 DAG nodes. I got it by
> manually reducing IR previously reduced by bugpoint. Is there a way to
> reduce it more, maybe on DAG level? Identifying the part of the DAG that
> causes the problem could be helpful.
>
> - Paweł
>
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