[LLVMdev] [ARM backend] SMLAL issue

[Jyoti Rajendra Allur]

Hi Tim/James,
In the following code, MUL, ADDS, ADC are combined to SMLAL only if 'b' and 'c' are promoted to long long type during multiplication. Shouldn't they be allowed to be combined to SMLAL 
even in the code as is without promoting b and c to long long type?

I found the reason for not combining to SMAL to be this, ADDS operand 0 has opcode not set as ISD::SMUL_LOHI even though operand 0 ie., R2 is a result of SMULBB as seen in the assembly.

long long
foo (long long a, int b, int c)
{
       return a + b * c;    ===> return a + (long long)b * (long long)c;

}
ldrb    r2, [r2]
ldrb    r3, [r3]
smulbb  r2, r3, r2
adds    r0, r2, r0
adc     r1, r1, #0
bx      lr

I have already checked in combine function in DAG combiner and visitADDC, ADDS node operand0 's opcode is not set to ISD::SMUL_LOHI. Only when b and c are typecasted to long long, operand0 opcode is set to  ISD::SMUL_LOHI
Is this a likely bug, if not is there a specific reason for designing it this way ?


Regards,
Jyoti Allur