[LLVMdev] i1 types in MergeConsecutiveStores

[Steve King]

Hello LLVM,

In DAGCombiner.cpp, MergeConsecutiveStores uses

int64_t ElementSizeBytes = MemVT.getSizeInBits()/8;

https://github.com/llvm-mirror/llvm/blob/master/lib/CodeGen/SelectionDAG/DAGCombiner.cpp#L10669

which is broken for i1 types where getSizeInBits() == 1.  My
out-of-tree target hits this case and eventually LLVM asserts in
Type.cpp.

Is there some reason MergeConsecutiveStores should not expect to see i1 types?

Thanks,
-steve