[LLVMdev] can we define a physical register for both integer and floating point

[Quentin Colombet]

Hi Xiangyang,

> On May 8, 2015, at 1:02 PM, Xiangyang Guo <xguo6 at ncsu.edu> wrote:
> 
> Hi,
> 
> My question sounds kind of silly, but can we define a physical register for both integer and floating point in LLVM backend?
> 
> In the section "Defining a Register Class" in tutorial "Writing an LLVM Backend", when we define a Register Class, we need to define the regType, which makes sense to me. But if both integer and floating point are 32 bits, why cannot we use a physical register to represent different types of numbers accordingly. 

I’m not sure what you mean here.
For a register class to handle different types is perfectly fine, e.g., on AArch64 both i32 and f32 can live in the same class:
def FPR32 : RegisterClass<"AArch64", [f32, i32], 32,(sequence "S%u", 0, 31)>;


> 
> And what if my backend does not have floating point physical register, but my IR has floating point virtual register?

You need to use a soft-float library.

Cheers,
Q.

> 
> Thanks
> 
> Xiangyang 
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