[LLVMdev] Indexed Load and Store Intrinsics - proposal

[Demikhovsky, Elena]

Craig tried to submit another table-gen patch, but his patch broke other targets.
As far as I know, Craig is still working on this patch.

-  Elena


-----Original Message-----
From: Hal Finkel [mailto:hfinkel at anl.gov] 
Sent: Sunday, March 15, 2015 16:15
To: Demikhovsky, Elena
Cc: llvmdev at cs.uiuc.edu; Hao Liu
Subject: Re: [LLVMdev] Indexed Load and Store Intrinsics - proposal

----- Original Message -----
> From: "Elena Demikhovsky" <elena.demikhovsky at intel.com>
> To: "Hao Liu" <haoliuts at gmail.com>
> Cc: llvmdev at cs.uiuc.edu
> Sent: Sunday, March 15, 2015 5:21:14 AM
> Subject: Re: [LLVMdev] Indexed Load and Store Intrinsics - proposal
> 
> hi Hao,
> 
> I started to upstream and the second patch is stalled under review 
> now.

Is this the patch that Craig was working on? I thought we had hit some problem with the TableGen changes. If it is just awaiting review, please ping it.

 -Hal

> 
> -  Elena
> 
> 
> -----Original Message-----
> From: Hao Liu [mailto:haoliuts at gmail.com]
> Sent: Friday, March 13, 2015 05:56
> To: Demikhovsky, Elena
> Cc: llvmdev at cs.uiuc.edu
> Subject: Re: [LLVMdev] Indexed Load and Store Intrinsics - proposal
> 
> Hi Elena,
> 
> I think such intrinsics are very useful.
> Do you have any plan to upstream them?
> 
> Thanks,
> -Hao
> 
> 2014-12-18 22:40 GMT+08:00 Demikhovsky, Elena
> <elena.demikhovsky at intel.com>:
> > Hi,
> >
> > Recent Intel architectures AVX-512 and AVX2 provide vector gather 
> > and/or scatter instructions.
> > Gather/scatter instructions allow read/write access to multiple 
> > memory addresses. The addresses are specified using a base address 
> > and a vector of indices.
> > We’d like Vectorizers to tap this functionality, and propose to do 
> > so by introducing new intrinsics:
> >
> > VectorValue = @llvm.sindex.load (BaseAddr, VectorOfIndices, Scale) 
> > VectorValue = @llvm.uindex.load (BaseAddr, VectorOfIndices, Scale) 
> > VectorValue = @llvm.sindex.masked.load (BaseAddr, VectorOfIndices, 
> > Scale, PassThruVal, Mask) VectorValue = @llvm.uindex.masked.load 
> > (BaseAddr, VectorOfIndices, Scale, PassThruVal, Mask)
> >
> > Semantics:
> > For i=0,1,…,N-1: if (Mask[i]) {VectorValue[i] = *(BaseAddr +
> > VectorOfIndices[i]*Scale) else VectorValue[i]=PassThruVal[i];}
> >
> > void @llvm.sindex.store (BaseAddr, VectorValue, VectorOfIndices,
> > Scale) void @llvm.uindex.store (BaseAddr, VectorValue, 
> > VectorOfIndices, Scale) void @llvm.sindex.masked.store (BaseAddr, 
> > VectorValue, VectorOfIndices, Scale, Mask) void 
> > @llvm.uindex.masked.store (BaseAddr, VectorValue, VectorOfIndices, 
> > Scale, Mask)
> >
> > Semantics:
> > For i=0,1,…,N-1: if (Mask[i]) {*(BaseAddr +
> > VectorOfIndices[i]*Scale)
> > = VectorValue[i];}
> >
> > VectorValue: any float or integer vector type.
> > BaseAddr: a pointer; may be zero if full address is placed in the 
> > index.
> > VectorOfIndices: a vector of i32 or i64 signed or unsigned integer 
> > values.
> > Scale: a compile time constant 1, 2, 4 or 8.
> > VectorValue, VectorOfIndices and Mask must have the same vector 
> > width.
> >
> > An indexed store instruction with complete or partial overlap in 
> > memory (i.e., two indices with same or close values) will provide 
> > the result equivalent to serial scalar stores from least to most 
> > significant vector elements.
> >
> > The new intrinsics are common for all targets, like recently 
> > introduced masked load and store.
> >
> > Examples:
> >
> > <16 x float> @llvm.sindex.load.v16f32.v16i32 (i8 *%ptr,   <16 x
> > i32> %index,
> > i32 %scale)
> > <16 x float> @llvm.masked.sindex.load.v16f32.v16i32  (i8 *%ptr, <16 
> > x i32>
> > %index,   <16 x float> %passthru, <16 x i1> %mask)
> > void @llvm.sindex.store.v16f32.v16i64(i8* %ptr, <16 x float>
> > %value,   <16 x
> > 164> %index, i32 %scale,  <16 x i1> %mask)
> >
> > Comments?
> >
> > Thank you.
> >
> >
> > Elena
> >
> >
> >
> >
> >
> > --------------------------------------------------------------------
> > -
> > Intel Israel (74) Limited
> >
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--
Hal Finkel
Assistant Computational Scientist
Leadership Computing Facility
Argonne National Laboratory
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