[LLVMdev] Inline Assembly: Memory constraints with offsets

[Krzysztof Parzyszek]

On 3/9/2015 5:22 AM, Daniel Sanders wrote:
>
> I've had some luck with this. It turns out that the ISD::INLINE_ASM node has a flag operand corresponding to each operand in the source code. It's used for storing things like the matched operand number for the [0-9]+ constraints,  the register class id for register constraints, etc. At first glance, the encoding looks full but it appears that when the lowest 3 bits are Kind_Mem (meaning it's a memory constraint), the upper 16-bits are never used. I've therefore used this gap to store a constraint ID which can then be inspected during instruction selection.

Fantastic!  Yes, this is one of the places that I looked at, but to my 
great disappointment the connection with the original constraint was not 
preserved.

Thanks for doing this!

-Krzysztof

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