[LLVMdev] TableGen question

[Dylan McKay]

As you suggested, it is based on the order of the declarations of the
variables in the class, and the order they are listed in the TableGen file.

See Writing an LLVM Backend/Instruction operand mapping
<http://llvm.org/docs/WritingAnLLVMBackend.html#instruction-operand-mapping>
.

Operands are assigned to unbound fields in the instruction in the order
they are defined. Fields are bound when they are assigned a value.

​

On Thu, Jun 25, 2015 at 5:28 PM, Mohamed Shafi <shafitvm at gmail.com> wrote:

> Hi,
>
> In tablegen file inside class we have variables declared inside a
> class. Say in PPC there is this
>
> class BForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string
> asmstr>
>   : I<opcode, OOL, IOL, asmstr, IIC_BrB> {
>   bits<7> BIBO;  // 2 bits of BI and 5 bits of BO.
>   bits<3>  CR;
>   bits<14> BD;
>
>
> How does the generator match each variable against an operand?
>
> For the corresponding PPCGenMCCodeEmitter.inc for this the entry is
>
>       // op: BIBO
>       op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
>       // op: CR
>       op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
>       // op: BD
>       op = getCondBrEncoding(MI, 2, Fixups, STI);
>
>
> How does the generator know that BIBO is op0 and CR is op1 and so on?
> Is it based on the order of the declarations of the variables in the class?
>
> Regards,
> Shafi
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