[LLVMdev] Register Allocation on IR

[kartikram3]

Hello all,

  I am trying to use the LLVM libraries to do register allocation on LLVM
IR code -- and output IR as the result.
There are two problems that arise when we try this :

a. The LLVM backend requires that one goes through all the steps
sequentially namely

     -- Instruction selection
     -- Scheduling and Formation
     -- SSA-based machine code optimizations
     -- Register allocations


       ...


      -- Code emission

Is it possible to emit IR from the 1st 3 stages and then do register
allocation on it ?
Normally, we would emit assembly based on the machine/ISA specifications
during
instruction selection.

b. I have llvm IR in the form of a DAG already. This was obtained by using
the llvm;;parseIRFile
function. I am not sure how to provide this ISA as an input to the backend
phases as they
seem to accept all kinds of other objects.

Are there any llvm functions that accept a DAG as input so that we can do
register allocation on it
subsequently ?


Note : This might look like a weird thing to do, but I want to do
simulations on IR and getting a
register-allocated IR is useful for that purpose.




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