[LLVMdev] Prevent instruction selection from clobbering an implicit data dependence through flags?

[Johnson, Nicholas Paul]

Hi,

In my target, certain intrinsic functions read or write the machine's flag registers.  Some of my benchmarks rely on implicit data dependences among such intrinsics.  How can I specify that these intrinsics carry this dependence, and that this dependence should be preserved through instruction selection?

For example, suppose I have this snippet of IR:
   ; (i) Write to flags
   tail call void @llvm.desradgcv2.mtcsr.n..s.i(i32 %written, i32 14)
   ; (ii) Some instructions in between
   %c = add i32 %a, %b
   %d = sub i32 0, %c
   ; (iii) Read from flags, i.e, %read := %written
   %read = tail call i32 @llvm.desradgcv2.mfcsr.s..i(i32 14)

During instruction selection, a pattern selects the 'mtcsr' and 'mfcsr' instructions for the two intrinsic calls (i) and (iii), respectively. There are two choices for the instructions in the middle (ii):
1. A verbatim translation into an 'add' and a 'sub' instruction.  I prefer this because it does not modify the flags in question.
2. The more idiomatic translation into 'negadd'.  In this context, this translation is incorrect because it clobbers the flag and disrupts the data dependence from (i) to (iii).

How can I specify that the second choice is incorrect in this instance because it clobbers the implicit flow.

Thank you,
Nick Johnson
D. E. Shaw Research