[LLVMdev] Scheduling unit latencies

[Hamza Halli]

Hello,
I’m working on a research project using LLVM. I Implemented a custom scheduler for a modified ARMv7A architecture and I need to set instruction latencies using defined values. For example : an ADD will take 2 cycles, a Load 8 cycles. I tried modifying the getInstrLatency method in the ARMBaseInstrInfo.cpp by setting latencies for each opcode (e.g. ARM::ADDrr). I also tried modifying the computeInstrLatency method in scheduleDAGSDNodes.cpp by setting the latencies for each ISD opcode. While debugging I still get the default latencies 1 cycle for integer instructions and 4 cycles for load. 
I’ m seeking help for this matter as it’s a critical step for my Master project.
I would be very grateful if anyone can give a hint.
Thank you
Hamza Halli