[LLVMdev] Adjusting Instruction Latencies

[hamza halli]

> 
> 
> Hello,
> I’m working on a custom instruction scheduling for a modified ARMv7A architecture. I’m trying to set manually the instruction latencies for this target without overwriting the pipeline itineraries by writing -for example- the following code in armbaseinstrinfo.cpp.
> By doing this I still get the default instruction latencies of the ARMv7 when I run my custom scheduler.
> Can somebody please help me on this matter?
> Thanks
> 
> unsigned ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
>                                            const MachineInstr *MI,
>                                            unsigned *PredCost) const {
>     
> 
>       
>     switch (MI->getOpcode()) {
> 
>         case ARM::ANDri:
>         case ARM::ANDrr:
>         case ARM::ANDrsi:
>         case ARM::ANDrsr:
>         case ARM::EORri:
>         case ARM::EORrr:
>         case ARM::EORrsi:
>         case ARM::EORrsr:
>         case ARM::ORRri:
>         case ARM::ORRrr:
>         case ARM::ORRrsi:
>         case ARM::ORRrsr:
>             return 1;
>             break;
>   
> 
>         case ARM::LSLi:
>         case ARM::LSLr:
>         case ARM::LSRi:
>         case ARM::LSRr:
>         case ARM::ADDri:
>         case ARM::ADDrr:
>         case ARM::ADCrsi:
>         case ARM::ADCrsr:
>         case ARM::ADCri:
>         case ARM::ADCrr:
>         case ARM::ADDrsi:
>         case ARM::ADDrsr:
>         case ARM::ADDSri:
>         case ARM::ADDSrr:
>         case ARM::ADDSrsi:
>         case ARM::ADDSrsr:
>         case ARM::ASRi:
>         case ARM::ASRr:
>         case ARM::CMNri:
>         case ARM::CMNzrr:
>         case ARM::CMNzrsi:
>         case ARM::CMNzrsr:
>         case ARM::CMPri:
>         case ARM::CMPrr:
>         case ARM::CMPrsi:
>         case ARM::CMPrsr:
>         case ARM::QADD:
>         case ARM::QADD16:
>         case ARM::QADD8:
>         case ARM::QASX:
>         case ARM::QDADD:
>         case ARM::QDSUB:
>         case ARM::QSAX:
>         case ARM::QSUB:
>         case ARM::QSUB16:
>         case ARM::QSUB8:
>         case ARM::RORi:
>         case ARM::RORr:
>         case ARM::RRX:
>         case ARM::RRXi:
>         case ARM::RSBri:
>         case ARM::RSBrr:
>         case ARM::RSBrsi:
>         case ARM::RSBrsr:
>         case ARM::RSBSri:
>         case ARM::RSBSrsi:
>         case ARM::RSBSrsr:
>         case ARM::RSCri:
>         case ARM::RSCrr:
>         case ARM::RSCrsi:
>         case ARM::RSCrsr:
>         case ARM::SADD16:
>         case ARM::SADD8:
>         case ARM::SASX:
>         case ARM::SBCri:
>         case ARM::SBCrr:
>         case ARM::SBCrsi:
>         case ARM::SBCrsr:
>         case ARM::SBFX:
>         case ARM::SEL:
>         case ARM::SETEND:
>             
>             
>         case ARM::SSAT:
>         case ARM::SSAT16:
>         case ARM::SSAX:
>         case ARM::SSUB16:
>         case ARM::SSUB8:
>         case ARM::SUBri:
>         case ARM::SUBrr:
>         case ARM::SUBrsi:
>         case ARM::SUBrsr:
>         case ARM::SUBS_PC_LR:
>         case ARM::SUBSri:
>         case ARM::SUBSrr:
>         case ARM::SUBSrsi:
>         case ARM::SUBSrsr:
>         case ARM::SWP:
>         case ARM::SWPB:
>         case ARM::SXTAB:
>         case ARM::SXTAB16:
>         case ARM::SXTAH:
>         case ARM::SXTB:
>         case ARM::SXTB16:
>         case ARM::SXTH:
>         case ARM::TEQri:
>         case ARM::TEQrr:
>         case ARM::TEQrsi:
>         case ARM::TEQrsr:
>         case ARM::TSTri:
>         case ARM::TSTrr:
>         case ARM::TSTrsi:
>         case ARM::TSTrsr:
>         case ARM::UADD16:
>         case ARM::UADD8:
>         case ARM::UASX:
>         case ARM::UBFX:
>         case ARM::UHADD16:
>         case ARM::UHADD8:
>         case ARM::UHASX:
>         case ARM::UHSAX:
>         case ARM::UHSUB16:
>         case ARM::UHSUB8:
>         case ARM::UQADD16:
>         case ARM::UQADD8:
>         case ARM::UQASX:
>         case ARM::UQSAX:
>         case ARM::UQSUB16:
>         case ARM::UQSUB8:
>         case ARM::USAD8:
>         case ARM::USADA8:
>         case ARM::USAT:
>         case ARM::USAT16:
>         case ARM::USAX:
>         case ARM::USUB16:
>         case ARM::USUB8:
>         case ARM::UXTAB:
>         case ARM::UXTAB16:
>         case ARM::UXTAH:
>         case ARM::UXTB:
>         case ARM::UXTB16:
>         case ARM::UXTH:
>             return 2;
>             break;
> 
> 		
				 
> 
> 
>         case ARM::LDRLIT_ga_pcrel_ldr:
>         case ARM::LDRrs:
>         case ARM::LDRSB:
>         case ARM::LDRSB_POST:
>         case ARM::LDRSB_PRE:
>         case ARM::LDRSBTi:
>         case ARM::LDRSBTr:
>         case ARM::LDRSH:
>         case ARM::LDRSH_POST:
>         case ARM::LDRSH_PRE:
>         case ARM::LDRSHTi:
>         case ARM::LDRSHTr:
>         case ARM::LDRT_POST:
>         case ARM::LDRT_POST_IMM:
>         case ARM::LDRT_POST_REG:
>    
>             return 8;
>             break;
>             
>         default:
>             
>             break;
>     }
>     
> 
> 
> 

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