[LLVMdev] TableGen Register Class not matching for MI in 3.6

[Ryan Taylor]

In LLVM 3.6,

 We have an instruction that uses a register class that is defined of
several different reg classes. In 3.4 this works fine but in 3.6 this is
broken.

For example, I have a mov instruction. mov can be executed between
different register types (ie gpr, index, base, etc..)

In 3.4, we would get something like this:

mov @a, %b1 // moving this immediate to a base register, which is what we
want

In 3.6, we now get this:

mov @a, %r0  // r0 = gpr
mov %r0, %b1 // b1 = base reg

The register class looks like this:

def ARegs : RegisterClass<"us", [i16], i16, (add GPRRegs, IndexRegs,
BaseRegs)>;

I have absolutely no idea why this is not matching any longer?

The fix here is to define an MI with explicit single register class (ie it
only allows PTRRegs as the destination).

This must be an issue with something else and not the tablegen but if that
was the case I'm not sure. Anyway help would be great, what should I be
looking at here?

Thanks.
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