[LLVMdev] TSFlags

[Sky Flyer]

Hi Krzystof,

regarding your first solution (creating separate instruction), is it
possible to somehow have cascading defm?
for example, let's suppose aaa is a 3-bit condition a, and bb is a 2-bit
condition b, all in one instruction, instead of having one multiclass with
2^5 conditions, is it possible to write 2^3 "a" conditions, and 2^2 "b"
conditions, and the rest taken care by the TableGen?

On Fri, Jul 10, 2015 at 5:59 PM, Krzysztof Parzyszek <
kparzysz at codeaurora.org> wrote:

> On 7/10/2015 10:23 AM, Sky Flyer wrote:
>
>> Many thanks for your prompt reply.
>>
>> I mean, imagine you have 3 bits for condition flags in your instruction
>> (e.g.  overflow, zero, carry set, ...) for conditional executions AND
>> there is no direct access to the Status Register, is it even possible to
>> implement such scenario?
>>
>>
> There doesn't have to be any explicit status register.  You can either
> create separate instructions for each condition, or have the condition as
> an extra operand.  Let's take "add" for example.  You could have several
> versions of add:
>   add     add unconditionally
>   addc    add if carry
>   addz    add if zero
>   addo    add if overflow
> and similarly for more complex conditions that your target could support,
> such as "carry or zero".  This has the disadvantage that the instruction
> set can get really large, but if the number of conditional instructions is
> small or if the possible conditions vary from one operation to another,
> this may be a viable solution.
> The other option is to model the condition as an operand (I think ARM does
> that).  So the add instruction could look like this:
>   R0 = add R1, R2, C
> where
>   C = 0: no conditions
>   C = 1: zero
>   C = 2: carry
>   C = 4: overflow
> etc.
>
> This way the instruction set would remain small, but it may involve
> special handling for it to work with the integrated assembler (if the
> native instruction format is different than what you chose).
>
> You could use the TSFlags to indicate for each instruction which condition
> this instruction can modify.  Taking the add again, it could modify all of
> the three: zero, carry and overflow, but a load could only modify zero (for
> example, specifics would depend on your target).
>
>
>
> -Krzysztof
>
>
> --
> Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted
> by The Linux Foundation
> _______________________________________________
> LLVM Developers mailing list
> LLVMdev at cs.uiuc.edu         http://llvm.cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev
>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20150727/a3bc2012/attachment.html>