[LLVMdev] fake an extend for "SEXT" signal

[kewuzhang]

HI Guys, 

I have a “normal” load instruction like the following:
"
 %2 = load i16 addressspace(1) * %1, align 2, !tbaa !10
“
where the metadata tbaa is telling me that the source is a signed short.
So I want to do a “signed load”  when I am lowering the Load operation.( LLVM now just tells me “load i16” without any sign or unsign info)

questions:
(1)  How could I pass the “sign” flag to customLowering?

(2) I wanted to “trick” llvm by “ inserting an extend, and followed by an truncate” instructions, so I am hoping that LLVM can send me a “SextLoad” and “Truncate”.
But LLVM is smart enough, it just ignores my effort. 

Is there anyway to “workaround” this problem?

best
kevin