[LLVMdev] Why change "sub x, 5" to "add x, -5" ?

[escha]

> On Jul 8, 2015, at 8:00 AM, Frédéric Heitzmann <frederic.heitzmann at gmail.com> wrote:
> 
> Dear all,
> 
> I have been working on a new LLVM backend. Some instructions, like sub, can take an positive constante, encoded into 5 bits thus lower than 32, and a register, as operands.
> Unfortunately, DAGCombiner.cpp changes patterns like 'sub x, 5' into 'add x,-5’.

Having a single canonical form makes optimizations easier, since you don’t have to check both possibilities at every optimization stage.

If you want to “revert" this sort of thing, you can do it at Select() time or PreprocessISelDAG(), which is what I did on an out-of-tree backend to turn add X, -C into sub X, C on selection time. This still lets all the intermediate optimizations take advantage of the canonicalization.

—escha