[LLVMdev] Why change "sub x, 5" to "add x, -5" ?

[Frédéric Heitzmann]

Dear all,

I have been working on a new LLVM backend. Some instructions, like sub, can
take an positive constante, encoded into 5 bits thus lower than 32, and a
register, as operands.
Unfortunately, DAGCombiner.cpp changes patterns like 'sub x, 5' into 'add
x,-5'.

Similarly, I found changes in some IR to IR passes, with no clear gain (at
least not clear to me), and even penalty for my specific ISA.

%add = add i32 %a, %b
%tobool = icmp eq i32 %add, 0

becomes :

%add = sub i32 0, %b
%tobool = icmp eq i32 %a, %

My question is not how to workaround those, but why such changes are done
for all targets, in DAG selection or in IR passes.
AFAIK, there is no target which has some better encoding with a negative
value than with a positive one.
And "sub" looks as costly as "add" to me.

Is there some other practical reason to perform this kind of change ?
Thanks for your highlights.

--
Frederic Heitzmann
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