[LLVMdev] Match immediate value in tablegen

[Xiaochu Liu]

I was trying to do a pattern matching for a rd+imm instruction in my own
backend.
It looks something like:
def: Pat<build_vector v2i16:$src1, v2i16:$src2, (OR (SLLI GPR: $src1,16),
GPR:$src2>;
OR takes two i32 in registers and SLLI takes one i32 in registers and an
immediate.

But the immediate '16' does not work here and I tried different ways. May I
know if any of you have any idea how to bake an immediate value (16) into
the tablegen?
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