[LLVMdev] Decoding context for instructions

[Colin LeMahieu]

I'm working on eliminating decoder conflicts for some instructions that have
different semantics and asm depending on if they're preceded by an extension
instruction.  I looked at the x86 decoder and it seems overkill for what I'm
trying to do but maybe it's the only way?

 

What I have is two instructions:

1)      {4 byte Instruction Encoding} -> "r0 = memw (gp + Addr6)"

2)      {4 byte Extension} {4 byte Instruction Encoding} -> "r0 = memw
(Addr32) "

 

The instruction encoding is ambiguous and needs the extension to
disambiguate which instruction it actually is though I'm getting tripped up
on how to get the decoder to do this.

 

Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, 
a Linux Foundation Collaborative Project

 

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