[LLVMdev] Machine LICM and cheap instructions?

[Krzysztof Parzyszek]

On Hexagon it's generally better to hoist everything out of the loop and 
then rematerialize cheap instructions if necessary.  Hexagon executes 
instruction in packets, and each extra instruction in the loop adds the 
likelihood of having more packets than necessary.  In case of small 
loops this can be particularly expensive and predicting packetization is 
extremely difficult without actually performing it.
The "hasLowDefLatency" is not really a good tool to model this, since 
cheap instructions are still cheap, and yet they are better hoisted out.

-Krzysztof

On 1/8/2015 3:45 PM, Hal Finkel wrote:
> Hi everyone,
>
> The MachineLICM pass has a heuristic such that, even in low-register-pressure situations, it will refuse to hoist "cheap" instructions out of loops. By default, when an itinerary is available, this means that all of the defined operands are available in at most 1 cycle. ARM overrides this, and provides this more-customized definition:
>
> bool ARMBaseInstrInfo::
> hasLowDefLatency(const InstrItineraryData *ItinData,
>                   const MachineInstr *DefMI, unsigned DefIdx) const {
>    if (!ItinData || ItinData->isEmpty())
>      return false;
>
>    unsigned DDomain = DefMI->getDesc().TSFlags & ARMII::DomainMask;
>    if (DDomain == ARMII::DomainGeneral) {
>      unsigned DefClass = DefMI->getDesc().getSchedClass();
>      int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
>      return (DefCycle != -1 && DefCycle <= 2);
>    }
>    return false;
> }
>
> So it won't hoist instructions that have defined operands ready in at most two cycles for general-domain instructions. Regardless, I don't understand the logic behind this heuristic. High-register-pressure situations are one thing, but why is it ever profitable in low-register-pressure situations not to hoist even "cheap" instructions out of loop bodies?
>
> Thanks again,
> Hal
>


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