[LLVMdev] Trouble with 3 operand instruction encodings

[Steve King]

Hello LLVM,

My target has a class of instructions taking 3 register operands with
syntax 'foo src2,src1,dst'.  The general case works fine, but
additional shorter encodings exist for cases where src1 is the same
register as dst.  I'm having trouble getting my AsmParser to pick the
short encodings.

Put another way, like we have the 'TwoOperandAliasConstraint' for 3
operand instructions, I'm trying to achieve something like a
'ThreeOperandAliasConstraint' for a 2 operand instruction.

Instructions with the short encodings are defined like this (paraphrased):

class RRR< bits<8> op, string mnemonic,
    (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),  []>{

    field bits<16> Inst;
    bits<4> src1;
    bits<4> src2;
    let AsmString = !strconcat(mnemonic, "\t$src2, $src1, $dst");
    let Inst{7-0} = op;
    let Inst{11-8} = src1;
    let Inst{15-12} = src2;
}

The obvious solution to me was add "let Constraints = "$src1 = $dst".
That fails because TableGen's AsmMatcherEmitter doesn't use
constraints to reject matches.  Instead src1 is "CVT_TIED" to dst and
the register in src1 is blindly stuffed into the dst register,
overwriting the actual dst register when src != dst.

How can I get the assembler to choose the short encodings when operand
conditions permit?

Thanks,
-steve