[LLVMdev] Indexed Load and Store Intrinsics - proposal

Mon Jan 5 08:13:53 PST 2015

On 22/12/14 14:05, Zaks, Ayal wrote:
>> Why shouldn't the IR representation simply be a load from a vector of arbitrary pointers?
> Such a load could indeed serve as a general form of a gather or scatter. As Elena responded, we can propose two distinct intrinsics: one with a vector of pointers, and another with (non-zero) base, a vector of indices, and a scale implicitly inferred from the element type.
>
> The motivation for the latter stems from vectorizing a load or store to "b[i]", where b is invariant. Broadcasting b and using a vector gep to feed a vector of pointers, to be pattern matched and folded later, may work. The alternative intrinsic proposed keeps b scalar and uses a vector of indices for i. In any case, it's important to recognize such common patterns, at-least for x86, so could deserve an x86 intrinsic. But it's a general pattern that could potentially serve other implementations; any other gathers to consider atm?
I think ARM supports a very limited form of gather/scatter through 
VLD2/3/4 and VST2/3/4 interleaved load and stores instructions.

For example, this instruction performs one gather load to d0, and 
another one to d1:

VLD2.8 {d0, d1}, [r0]

Using the proposed 'vector index' intrinsics, this would translate to IR 
like:

%scale = i32 1
%indices0 = <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 
12, i32 14>
%indices1 = <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 
13, i32 15>
%d0 = @llvm.uindex.load(i8* %addr.r0, <8 x i32> %indices0, i32 %scale) ; 
<8 x i8>
%d1 = @llvm.uindex.load(i8* %addr.r0, <8 x i32> %indices1, i32 %scale) ; 
<8 x i8>

Same for the 3-element variant:

VLD3.8 {d0, d1, d2}, [r0]

%scale = i32 1
%indices0 = <8 x i32> <i32 0, i32 3, i32 6, i32 9, i32 12, i32 15, i32 
18, i32 21>
%indices1 = <8 x i32> <i32 1, i32 4, i32 7, i32 10, i32 13, i32 16, i32 
19, i32 22>
%indices2 = <8 x i32> <i32 2, i32 5, i32 8, i32 11, i32 14, i32 17, i32 
20, i32 23>
%d0 = @llvm.uindex.load(i8* %addr.r0, <8 x i32> %indices0, i32 %scale) ; 
<8 x i8>
%d1 = @llvm.uindex.load(i8* %addr.r0, <8 x i32> %indices1, i32 %scale) ; 
<8 x i8>
%d2 = @llvm.uindex.load(i8* %addr.r0, <8 x i32> %indices2, i32 %scale) ; 
<8 x i8>

This pattern comes up with code that converts data from AoS to SoA, for 
example when doing whole-function vectorization (e.g. if b is an array 
of vectors, due to scalarization).

It is quite limited tough (sequential indices, fixed scale), and 
probably more difficult to match than single intrinsics.

Pierre-Andre

>
> Documentation indeed needs to be provided.
>
> Ayal.
>
>
> -----Original Message-----
> From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of Philip Reames
> Sent: Sunday, December 21, 2014 20:25
> To: dag at cray.com; Demikhovsky, Elena
> Cc: Khasanov, Robert; llvmdev at cs.uiuc.edu
> Subject: Re: [LLVMdev] Indexed Load and Store Intrinsics - proposal
>
>
> On 12/18/2014 11:56 AM, dag at cray.com wrote:
>> "Demikhovsky, Elena" <elena.demikhovsky at intel.com> writes:
>>
>>> Semantics:
>>> For i=0,1,…,N-1: if (Mask[i]) {*(BaseAddr + VectorOfIndices[i]*Scale)
>>> = VectorValue[i];}
>>> VectorValue: any float or integer vector type.
>>> BaseAddr: a pointer; may be zero if full address is placed in the
>>> index.
>>> VectorOfIndices: a vector of i32 or i64 signed or unsigned integer
>>> values.
>> What about the case of a gather/scatter where the BaseAddr is zero and
>> the indices are pointers?  Must we do a ptrtoint?  llvm.org is down at
>> the moment but I don't think we currently have a vector ptrtoint.
> I would be opposed to any representation which required the introduction of ptrtoint casts by the vectorizer.  If it were the only option available, I could be argued around, but I think we should try to avoid this.
>
> More generally, I'm somewhat hesitant of representing a scatter with explicit base and offsets at all.  Why shouldn't the IR representation simply be a load from a vector of arbitrary pointers?  The backend can pattern match the actual gather instructions it supports and scalarize the rest.  The proposal being made seems very specific to the current generation of x86 hardware.
>
> p.s. Where is the documentation for the existing mask load intrinsics?
> I can't find it with a quick search through the LangRef.
>
> Philip
>
>
>
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