[llvm-dev] Tablegen definition question

[Sky Flyer via llvm-dev]

Hello James,

It was actually EncoderMethod.
I implemented the function that uses this logic (borrowed from ARM) and it
works. Thanks again for your help :-)

  const MCOperand &MO  = MI.getOperand(OpIdx);
  const MCOperand &MO1 = MI.getOperand(OpIdx + 1);



On Mon, Dec 14, 2015 at 2:46 PM, James Molloy <james at jamesmolloy.co.uk>
wrote:

> Hi,
>
> That's what the DecoderMethod is for. Similarly ParserMatchClass for the
> asm parser and PrintMethod for the asm printer:
>
> def CondCodeOperand : AsmOperandClass { let Name = "CondCode"; }
> def pred : PredicateOperand<OtherVT, (ops i32imm, i32imm),
>                                      (ops (i32 14), (i32 zero_reg))> {
>   let PrintMethod = "printPredicateOperand";
>   let ParserMatchClass = CondCodeOperand;
>   let DecoderMethod = "DecodePredicateOperand";
> }
>
> James
>
> On Mon, 14 Dec 2015 at 13:44 Sky Flyer <skylake007 at googlemail.com> wrote:
>
>> But one question!
>>
>> imagine I define *cond* as a type of Xpred (Xpred:$cond)
>> and in the instruction, for instance *bits<6> cond*.
>> How can I assign the first i32imm to the 4 MSB of cond and the second
>> i32imm to the 2 LSB? :-/
>>
>> Now:
>>
>> Xpred:$cond
>> bits<6> cond;
>> Inst{5-0} = cond;
>>
>> Desired:
>>
>> Xpred:$cond;
>> bits<6> cond;
>> Inst{5-2} = cond.ops[0];
>> Inst{1-0} = cond.ops[1];
>>
>>
>>
>> On Mon, Dec 14, 2015 at 12:24 PM, Sky Flyer <skylake007 at googlemail.com>
>> wrote:
>>
>>> Hello James,
>>>
>>> that was also what I've planned to do but just wasn't sure. Thanks for
>>> that.
>>>
>>>
>>> On Mon, Dec 14, 2015 at 11:52 AM, James Molloy <james at jamesmolloy.co.uk>
>>> wrote:
>>>
>>>> Hi,
>>>>
>>>> You can't nest operands like that - it must be a flattened list. So:
>>>>
>>>> def *Xpred* : PredicateOperand<OtherVT, (ops *i32imm, i32imm*, i32imm),
>>>> (ops (i32 14), (i32 zero_reg))> {...}
>>>>
>>>> On Mon, 14 Dec 2015 at 10:21 Sky Flyer via llvm-dev <
>>>> llvm-dev at lists.llvm.org> wrote:
>>>>
>>>>> Hi All,
>>>>>
>>>>> In ARMInstFormats.td predicate is defined this way:
>>>>>
>>>>>
>>>>>
>>>>> *def pred : PredicateOperand<OtherVT, (ops i32imm, i32imm),*
>>>>> *(ops (i32 14), (i32 zero_reg))> {...}*
>>>>>
>>>>>
>>>>> I use the same definition in my code. But I have another version of
>>>>> predicate which is exactly the same but it is a condition code plus a
>>>>> quantifier! (e.g. Xpred = (pred + i32imm)).
>>>>>
>>>>> I was wondering how we can define a sub sub operand, something like
>>>>> this:
>>>>>
>>>>> def *Xpred* : PredicateOperand<OtherVT, (ops *pred*, i32imm),
>>>>> (ops (i32 14), (i32 zero_reg))> {...}
>>>>>
>>>>> I don't know how clear I explained, but can someone recommend a
>>>>> solution?
>>>>>
>>>>> Cheers,
>>>>> ES
>>>>>
>>>>>
>>>>> _______________________________________________
>>>>> LLVM Developers mailing list
>>>>> llvm-dev at lists.llvm.org
>>>>> http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev
>>>>>
>>>>
>>>
>>
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