[llvm-dev] Tablegen definition question

Sky Flyer via llvm-dev llvm-dev at lists.llvm.org
Mon Dec 14 02:21:26 PST 2015

Hi All,

In ARMInstFormats.td predicate is defined this way:

*def pred : PredicateOperand<OtherVT, (ops i32imm, i32imm),*
*(ops (i32 14), (i32 zero_reg))> {...}*

I use the same definition in my code. But I have another version of
predicate which is exactly the same but it is a condition code plus a
quantifier! (e.g. Xpred = (pred + i32imm)).

I was wondering how we can define a sub sub operand, something like this:

def *Xpred* : PredicateOperand<OtherVT, (ops *pred*, i32imm),
(ops (i32 14), (i32 zero_reg))> {...}

I don't know how clear I explained, but can someone recommend a solution?

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