[llvm-dev] Question Regarding SystemZ Implementation Missing Instructions
Phil via llvm-dev
llvm-dev at lists.llvm.org
Thu Dec 3 19:52:44 PST 2015
I had some questions regarding the SystemZ implementation and missing instructions.
I've been comparing the IBM z/Architecture Reference Summary (SA22-7871-08) to the output of
"llvm-tblgen SystemZ.td -print-enums -class=Instruction" and noticed that there's 525 missing instructions.
For example, if I look at instruction "M" (page 16, Multiply (64 <- 32)) with opcode 0x5c, this instruction isn't listed in the output. Digging further I confirmed this instruction isn't implemented within SystemZInstrInfo.td (or any file in the llvm/lib/Target/SystemZ folder).
Am I missing something or could this instruction be implemented elsewhere within llvm?
I've also done cursory searching, here's a random selection of 12 more, out of 525, instructions that I've confirmed aren't implemented:
- ALSI Add Logical with Signed Immediate
- BAKR Branch and Stack
- BAL Branch and Link
- BALR Branch and Link
- CEGR Convert from Fixed (SH <- 64)
- LFPC Load FPC
- MDR Multiply (LH)
- STCMY Store Characters under Mask (low)
- STMY Store Multiple (32)
- TAR Test Access
- VACCC Vector Add With Carry Compute Carry (NEW since 2012)
- VFENE Vector Find Element Not Equal (NEW since 2012)
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