[llvm-dev] Update liveIntervals after inserting a MachineBasicBlock

Ziqiang Patrick Huang via llvm-dev llvm-dev at lists.llvm.org
Tue Aug 18 11:08:05 PDT 2015

Hi all,

Suppose I have two basic blocks A->B and I want to insert a new basic block
C between A and B, so that A->C->B. Right now I'm able to insert the block
and correctly update the SlotIndexes. But I'm having trouble updating the
LiveIntervals, so at very least I have to make sure all registers that are
live in into B are live through C.

Suppose after inserting C the Slot Index range for the 3 blocks are

A [0, 20]
C [28, 40]
B [44, 60]

and the liveInterval of %verg 1 is (4r, 52r). So right now the liveInterval
already covers C, but later I'm failing an assertion in
LiveIntervals::shrinkToUses() function.

// Make sure VNI is live-out from the predecessors.

      for (MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(),
           PE = MBB->pred_end(); PI != PE; ++PI) {
        if (!LiveOut.insert(*PI))
        SlotIndex Stop = getMBBEndIdx(*PI);
        assert(li->getVNInfoBefore(Stop) == VNI &&
               "Wrong value out of predecessor");
        WorkList.push_back(std::make_pair(Stop, VNI));

so I print out li here and it's (4r, 28B) [44B, 52r), so at some point the
live interval of %vreg 1 is split and LLVM has no idea that register live
through C, which means I must have missed updating something when I create

I'm doing this in MachineScheduler Pass,

Dear Cameron, I CC you because when I google to find some clue, I noticed
you submit a patch for MachineBasicBlock::SplitCriticalEdge() on updating
liveIntervals, so I thought maybe you might be able to help me. I tried the
same method you did but still did not pass that assertion.

Thanks in advance,
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