[llvm-dev] ARM: Predicated returns considered analyzable?

[Krzysztof Parzyszek via llvm-dev]

Hello,

The function ARMBaseInstrInfo::AnalyzeBranch contains the following 
piece of code:

      } else if (I->isReturn()) {
        // Returns can't be analyzed, but we should run cleanup.
        CantAnalyze = !isPredicated(I);
      } else {

This could lead to cases where for a block that ends with a
conditional return, AnalyzeBranch returns false (i.e. analyzed),
both TBB and FBB are nullptr, and Cond is empty, that is, indicating
no branches at all.  Since returns do not have any additional CFG edges 
corresponding to the "returning", it may happen that the block will 
appear to have no branches and a single fall-through successor.  This 
may lead to merging the block with its successor, and an example of this 
is test/CodeGen/Thumb2/thumb2-ifcvt2.ll:

$ llc < test/CodeGen/Thumb2/thumb2-ifcvt2.ll -mtriple=thumbv7-apple-ios

# *** IR Dump After If Converter ***:
# Machine code for function foo: Post SSA
Frame Objects:
   fi#0: size=4, align=4, at location [SP-4]
   fi#1: size=4, align=4, at location [SP-8]
Function Live Ins: %R0, %R1

BB#0: derived from LLVM BB %entry
     Live Ins: %R0 %R1 %R7 %LR %LR %R7
         %SP<def,tied1> = t2STMDB_UPD %SP<tied0>, pred:14, pred:%noreg, 
%R7<kill>, %LR<kill>; flags: FrameSetup
         CFI_INSTRUCTION <call frame instruction>; flags: FrameSetup
         CFI_INSTRUCTION <call frame instruction>; flags: FrameSetup
         CFI_INSTRUCTION <call frame instruction>; flags: FrameSetup
         %R7<def> = tMOVr %SP<kill>, pred:14, pred:%noreg; flags: FrameSetup
         CFI_INSTRUCTION <call frame instruction>; flags: FrameSetup
         t2CMPri %R1<kill>, 0, pred:14, pred:%noreg, %CPSR<imp-def>
         t2CMPri %R0<kill>, 3, pred:1, pred:%CPSR, %CPSR<imp-def>, 
%CPSR<imp-use,undef>
-->     %SP<def,tied1> = t2LDMIA_RET %SP<tied0>, pred:8, pred:%CPSR, 
%R7<def>, %PC<def>, %SP<imp-use,undef>, %R7<imp-use,undef>, 
%PC<imp-use,undef>
         tBLXi pred:14, pred:%noreg, <ga:@bar>, <regmask>, 
%LR<imp-def,dead>, %SP<imp-use>, %SP<imp-def>, %R0<imp-def,dead>
         %SP<def,tied1> = t2LDMIA_RET %SP<tied0>, pred:14, pred:%noreg, 
%R7<def>, %PC<def>

Here the instruction t2LDMIA_RET is a terminator and yet it's followed 
by a non-terminator tBLXi.  This looks wrong.  Does anyone have any 
comments on this?


-Krzysztof


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