[LLVMdev] MMX/SSE subtarget feature in IR

[suyog sarda]

Hi Kevin,

Thanks for the reply.

The target-cpu generated in IR is pentium4 which has SSE. But we are
overriding that by specifying features as "+mmx, -sse" which means we are
disallowing SSE and only allowing MMX.

I further tried to see if it can vectorize (SLP) with MMX and without SSE.
At the start of SLP vectorization, it checks if target has vector registers
or not. For above IR, we have MMX on and SSE off. If I am not wrong, target
with MMX feature has vector registers, and hence it should vectorize. But
it is not vectorizing the IR.

Am I missing something here?

Regards,
Suyog Sarda
On 11 Apr 2015 01:31, "Smith, Kevin B" <kevin.b.smith at intel.com> wrote:

>  Your clang invocation below works for me, and generates target triple in
> the llvm IR of
>
> i386.
>
>
>
> And then in the specific options for the functions it generates the
> following:
>
> ; Function Attrs: nounwind
>
> define float @foo() #0 {
>
> entry:
>
>   ret float 1.000000e+00
>
> }
>
>
>
> attributes #0 = { nounwind "less-precise-fpmad"="false"
> "no-frame-pointer-elim"=
>
> "true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false"
> "no-nans-fp-ma
>
> th"="false" "stack-protector-buffer-size"="8" "target-cpu"="pentium4"
> "target-fe
>
> atures"="+mmx,-sse" "unsafe-fp-math"="false" "use-soft-float"="false" }
>
>
>
> The attributes indicate to allow mmx, disallow sse, so this certainly
> looks like it might work. I don't
>
> know whether work has been done to specifically do something special for
> this combination, since
>
> use of MMX overlaps with X87 floating point state.  The processors that
> support mmx, but not SSE
>
> would be
>
>
>
> Pentium w MMX processor
>
> Pentium II family processors
>
>
>
> Kevin
>
>
>
> *From:* suyog sarda [mailto:sardask01 at gmail.com]
> *Sent:* Friday, April 10, 2015 2:51 AM
> *To:* Smith, Kevin B
> *Cc:* Sanjay Patel; David Majnemer; LLVM Developers Mailing List
> *Subject:* Re: [LLVMdev] MMX/SSE subtarget feature in IR
>
>
>
> Hi Kevin,
>
>
>
> I had another query for 32 bit x86. (Apology for being naive)
>
>
>
> I guess the default CPU on 32-bit x86 is 'pentium4', which has SSE as
> seen in getX86TargetCPU() in tools/clang/lib/Driver/Tools.cpp:
>
> static const char *getX86TargetCPU(const ArgList &Args,
>
>                                    const llvm::Triple &Triple) {
>
> ...
>
>   // Everything else goes to x86-64 in 64-bit mode.
>
>   if (Is64Bit)
>
>     return "x86-64";
>
>
>
>   switch (Triple.getOS()) {
>
>   case llvm::Triple::FreeBSD:
>
>   case llvm::Triple::NetBSD:
>
>   case llvm::Triple::OpenBSD:
>
>     return "i486";
>
>   case llvm::Triple::Haiku:
>
>     return "i586";
>
>   case llvm::Triple::Bitrig:
>
>     return "i686";
>
>   default:
>
>     // Fallback to p4.
>
>     return "pentium4";
>
>   }
>
> }
>
>
>
> Is there any 32-bit CPU with MMX feature but without SSE feature?
>
>
>
> Can it be done as follows :
>
>
>
> $ clang 1.c -mmmx -mno-sse -emit-llvm -S -target i386.
>
>
>
> My intention is to generate IR for x86 32 bit CPU with MMX feature but
> without SSE feature and further investigate if vectorization triggers for
> 32 bit architecture with MMX feature only.
>
>
>
> Thanks.
>
>
>
> Regards,
>
> Suyog Sarda
>
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