[LLVMdev] Unreachable br in IR but still seems to be executed

[Dave Pitsbawn]

I'm trying to implement a continue statement like in C

                if (i % 2 == 0)
                {
                    i = i + 1;
                    continue;
                }
                else
                {
                    i = i + 1;
                }

My code generates IR like this, because of how I visit my AST, so when I
encounter a continue or break statement I go and find the corresponding
while.

I was hoping LLVM would do the right thing which is ignore the unreachable
IR (br label %if.end). But it seems to somehow get to execute statements
after my br

I've marked it with "SHOULD NOT HAPPEN"
define i32 @Main() {
entry:
  %i = alloca i32
  %loopCounter = alloca i32
  store i32 0, i32* %i
  store i32 0, i32* %loopCounter
  br label %while.cond
while.cond:                                       ; preds = %if.end,
%if.then, %
entry
  %0 = load i32* %i
  %cmptmp = icmp slt i32 %0, 100
  br i1 %cmptmp, label %while.body, label %while.end
while.body:                                       ; preds = %while.cond
  %1 = load i32* %i
  %modtmp = srem i32 %1, 2
  %cmptmp1 = icmp eq i32 %modtmp, 0
  br i1 %cmptmp1, label %if.then, label %if.else
while.end:                                        ; preds = %while.cond
  %2 = load i32* %loopCounter
  ret i32 %2
if.then:                                          ; preds = %while.body
  %3 = load i32* %i
  %add = add i32 %3, 1
  store i32 %add, i32* %i
  br label %while.cond
  %4 = load i32* %I                      <----------- SHOULD NOT HAPPEN
  %sub = sub i32 %4, 1
  store i32 %sub, i32* %i
  br label %if.end
if.else:                                          ; preds = %while.body
  %5 = load i32* %i
  %add2 = add i32 %5, 1
  store i32 %add2, i32* %i
  br label %if.end
if.end:                                           ; preds = %if.else,
%if.then
  %6 = load i32* %loopCounter
  %add3 = add i32 %6, 1
  store i32 %add3, i32* %loopCounter
  br label %while.cond
after_ret:                                        ; No predecessors!
  ret i32 0
}
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