[LLVMdev] Problem in X86 backend

[Rinaldini Julien]

Hum, in fact, I'm still a bit lost ;)

It seems to works in -O0, but in -O1, -O2 and -O3, I got this error (+ the dump of the function):

# Machine code for function foo: Post SSA
Function Live Ins: %RDI in %vreg7

BB#0: derived from LLVM BB %entry
    Live Ins: %RDI
        %vreg7<def> = COPY %RDI; GR64:%vreg7
        %vreg1<def> = MOV64rm %vreg7, 1, %noreg, 8, %noreg; mem:LD8[%args.03](tbaa=<badref>) GR64:%vreg1,%vreg7
        TEST64rr %vreg1, %vreg1, %EFLAGS<imp-def>; GR64:%vreg1
        JE_4 <BB#3>, %EFLAGS<imp-use,kill>
    Successors according to CFG: BB#3(12) BB#1(20)

BB#1: 
    Predecessors according to CFG: BB#0
        %vreg9<def> = COPY %vreg1; GR64:%vreg9,%vreg1
        %vreg10<def> = COPY %vreg7; GR64:%vreg10,%vreg7
        %vreg0<def> = LEA64r %vreg7, 1, %noreg, 8, %noreg; GR64:%vreg0,%vreg7
        %vreg11<def> = COPY %vreg0; GR64:%vreg11,%vreg0
    Successors according to CFG: BB#2

BB#2: derived from LLVM BB %while.body
    Predecessors according to CFG: BB#2 BB#1
        %vreg4<def> = COPY %vreg11; GR64:%vreg4,%vreg11
        %vreg3<def> = COPY %vreg10; GR64:%vreg3,%vreg10
        %vreg2<def> = COPY %vreg9; GR64:%vreg2,%vreg9
        ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
        %RDI<def> = COPY %vreg2; GR64:%vreg2
        CALL64pcrel32 <ga:@puts>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSP<imp-def>, ...
        ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
        %vreg6<def> = MOV64rm %vreg3, 1, %noreg, 16, %noreg; mem:LD8[%args.0](tbaa=<badref>) GR64:%vreg6,%vreg3
        %vreg5<def> = COPY %vreg3; GR64:%vreg5,%vreg3
        %vreg5<def,tied1> = ADD64ri8 %vreg5<tied0>, 16, %EFLAGS<imp-def,dead>; GR64:%vreg5
        TEST64rr %vreg6, %vreg6, %EFLAGS<imp-def>; GR64:%vreg6
        %vreg9<def> = COPY %vreg6; GR64:%vreg9,%vreg6
        %vreg10<def> = COPY %vreg4; GR64:%vreg10,%vreg4
        %vreg11<def> = COPY %vreg5; GR64:%vreg11,%vreg5
        JNE_4 <BB#2>, %EFLAGS<imp-use,kill>
        JMP_4 <BB#3>
    Successors according to CFG: BB#3(4) BB#2(124)

BB#3: derived from LLVM BB %while.end
    Predecessors according to CFG: BB#0 BB#2
    Successors according to CFG: BB#4

BB#4: derived from LLVM BB %while.end
    Predecessors according to CFG: BB#3 BB#5
        CMP64rr %RDI, %RBP<kill>, %EFLAGS<imp-def>
        JE_4 <BB#6>, %EFLAGS<imp-use,kill>
    Successors according to CFG: BB#6 BB#5

BB#5: derived from LLVM BB %while.end
    Predecessors according to CFG: BB#4
        MOV32mi %RDI<kill>, 1, %noreg, 0, %noreg, 0
        JMP_4 <BB#4>
    Successors according to CFG: BB#4

BB#6: derived from LLVM BB %while.end
    Predecessors according to CFG: BB#4
        RETQ

# End machine code for function foo.

*** Bad machine code: Using an undefined physical register ***
- function:    foo
- basic block: BB#4 while.end (0x46c4840)
- instruction: CMP64rr %RDI, %RBP<kill>, %EFLAGS<imp-def>
- operand 0:   %RDI

*** Bad machine code: Using an undefined physical register ***
- function:    foo
- basic block: BB#4 while.end (0x46c4840)
- instruction: CMP64rr %RDI, %RBP<kill>, %EFLAGS<imp-def>
- operand 1:   %RBP<kill>

*** Bad machine code: Using an undefined physical register ***
- function:    foo
- basic block: BB#5 while.end (0x46c48f0)
- instruction: MOV32mi %RDI<kill>, 1, %noreg, 0, %noreg, 0
- operand 0:   %RDI<kill>


Cheers