[LLVMdev] Adding masked vector load and store intrinsics

[dag at cray.com]

"Smith, Kevin B" <kevin.b.smith at intel.com> writes:

>> How would one express such semantics in LLVM IR with this intrinsic?
>> By definition, %data anmd %passthrough are different IR virtual
>> registers and there are no copy instructions in LLVM IR.
>
> You never need to express this semantic in LLVM IR, because in SSA
> form they are always different SSA defs for the result of the
> operation versus the inputs to the operation.  Someplace late in the
> CG needs to handle this, in exactly an analogous fashion as it already
> has to handle this for mapping to regular X86 two address code.

Ok, I think that works.  I was concerned there may be some reason to
express this at the IR level for, say, AVX-512 because of masks but I
think you're right, the normal two-operand handling scheme can take care
of it.

                                     -David