[LLVMdev] memory scopes in atomic instructions

[Owen Anderson]

> On Nov 18, 2014, at 2:35 PM, Chandler Carruth <chandlerc at google.com> wrote:
> 
> 
> On Fri, Nov 14, 2014 at 1:09 PM, Sahasrabuddhe, Sameer <sameer.sahasrabuddhe at amd.com <mailto:sameer.sahasrabuddhe at amd.com>> wrote:
> 1. Update the synchronization scope field in atomic instructions from a
>    single bit to a wider field, say 32-bit unsigned integer.
> 
> I think this should be an arbitrary bit width integer. I think baking any size into this is a mistake unless that size is "1”.

...
> If we go with your proposed constraint below, I think it is essential to model single-thread-scope as the maximum integer. It should be a strict subset of all inter-thread scopes.

These seem mutually contradictory.

>  
> 5. Possibly add the following constraint on memory scopes: "The scope
>    represented by a larger value is nested inside (is a proper subset
>    of) the scope represented by a smaller value." This would also imply
>    that the value used for single-thread scope must be the largest
>    value used by the target.
>    This constraint on "nesting" is easily satisfied by HSAIL (and also
>    OpenCL), where synchronization scopes increase from a single
>    work-item to the entire system. But it is conceivable that other
>    targets do not have this constraint. For example, a platform may
>    define synchronization scopes in terms of overlapping sets instead
>    of proper subsets.
> 
> I think this is the important thing to settle on in the design. I'd really like to hear from a diverse set of vendors and folks operating in the GPU space to understand whether having this constraint is critically important or problematic for any reasons.

I am not aware of any systems (including GPUs) that would need non-nested memory scopes.  If such exist, I might expect them to be some kind of clustered NUMA HPC machine.

—Owen


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