[LLVMdev] [RFC] TableGen help for relaxation

[Steve King]

Hello LLVM,

My target has a complex relaxation hierarchy.  Perhaps a modest
TableGen extension would help consolidate most of the work involved in
choosing a relaxed opcode.  I also notice the x86 relaxation code with
a comment wondering if TableGen could improve life.

Does the following outline sound interesting?

1) Add a new field of type 'Instruction' to the Instruction class
called "RelaxedInstr"

2) Target instructions optionally set RelaxedInstr, as in:

def JMP32 : Instruction<stuff>;  // no relaxation from here
def JMP8 : Instruction<stuff> {
      let RelaxedInstr = JMP32;  // relax to 32-bit jmp
}

3) The tblgen -gen-instr-info processor uses RelaxedInstruction to
create the RelaxedOpcode field for the corresponding MCInst.  The
RelaxedOpcode field contains the target specific opcode (an
enumeration value) of the specified RelaxedInstr.

4) From C++, targets access the RelaxedOpcode field as needed, akin to
TSFlags.  This eliminates the headaches of massive opcode switch
statements in targets like mine.

It's unclear to me how to handle the default value of an 'Instruction'
when no relaxation exists.

Regards,
-steve