[LLVMdev] Custom constraints in instruction schedulers

[Pierre-Andre Saulais]

Hi Sergey,

On 07/11/14 09:54, Sergey Dmitrouk wrote:
> Hello Andrew, Dave,
>
> during review of http://reviews.llvm.org/D6054 it was suggested that I
> ask you of a better approach using instruction scheduler.
>
> What I'm trying to do
> ---------------------
>
> Ensuring that ldp-stp instruction pair used to implement inlined memcpy()
> have no instructions between them.
>
> Approaches that didn't work
> ---------------------------
>
> In general:
>
> * gluing
> * using TokenFactor node per load/store pair
> * pseudo-instruction (couldn't implement due to the need of temporary
>    registers)
I haven't followed the review, so that I don't know whether this would 
work for you or not. Did you consider adding a 'def' operand to your 
pseudo-instruction? That should allow you to allocate a register for 
your temporary value. Of course, this only works if the pseudo 
instruction is created before register allocation.
>
> In fact there were a lot of different modifications and mixes, none of
> which worked as expected.
>
> What works
> ----------
>
> Manual reordering after all instruction scheduler passes.
>
> How scheduler could help
> ------------------------
>
> I guess checking for registers and offset is enough to check for this
> special case, then scheduler could assume latency of load pair instruction
> to be zero in this particular case.
>
> I couldn't find a way to configure instruction scheduler in such a way.
> My questions is: is it actually possible or easy to add?  Scheduler
> implementation doesn't seem to provide hooks to make such exceptions.
>
> Best regards,
> Sergey
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Pierre-Andre Saulais
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