[LLVMdev] Question about callee saved registers in x86

[Vadim Chugunov]

On Fri, May 30, 2014 at 7:34 PM, Sanjoy Das <sanjoy at azulsystems.com> wrote:

> Hi!
>
> On May 30, 2014, at 5:12 PM, Vadim Chugunov <vadimcn at gmail.com> wrote:
>
> > Hi,
> > I have a related question.  The spilled x86 GPRs are assigned positive
> frame indices, which seems problematic in cases when stack needs to be
> realigned:  they are pushed before stack is re-aligned, so they cannot be
> addressed relative to the stack pointer (because there is a random gap
> caused by SP re-alignment).
> >
> > Shouldn't they be assigned negative indices, i.e. be fixed objects, in
> which case they can be addressed relative to BP?
>
> Does llvm actually emit code to directly access the callee saved
> registers?  As long as all llvm does is push them on entry and pop them on
> exit, you don't really care very much about offsets.
>
> As far as DWARF information is concerned, I'd expect the locations of the
> callee saved register spills be in terms of the CFA (Canonical Frame
> Address), and as long as llvm emits a correct expression to calculate the
> CFA at all points of the function body, DWARF readers should do fine.
>
> My initial point of confusion was that it seems llvm has some internal
> discrepancies about what slots CSRs get mapped to -- the actual code seems
> to push them in an different order than the they are assigned slots on the
> stack.  This gets corrected later on, and we do get accurate .cfi
> directives, so I figured that this may be some convention that I had missed.
>
> However, (thanks to Pasi's hint) there are cases where llvm generates
> incorrect .cfi directives, and this leads me to think that the issue is, in
> fact, the lack of co-ordination between the code that emits the PUSH
> instructions and the code that assigns stack slots to the CSR frame indices.
>

If CSR indices corresponded to the actual locations where the registers are
saved, it might be possible to use CSR info and getFrameIndexReference() to
generate offsets for CFI directives, and everything would be in sync pretty
much automatically, no?

Anyhow, I am interested in this because I am trying to implement SEH unwind
info emission for 64 bit Windows.  Currently, the XMM registers are being
spilled into non-fixed frame slots, and if the stack is realigned, they end
up on the wrong side of the "realignment gap".   This makes generation of
SEH info (which is far less expressive than DWARF CFI) very challenging.
Things would be much easier if XMMs were saved above the gap, and thus
addressable via the base pointer.

Does anybody know if it is possible to assign callee-saved registers to
fixed frame slots?   Any ideas about how to achieve that?    Would it be ok
to simply re-write CSR info inside spillCalleeSavedRegisters()?

Vadim
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