[LLVMdev] Instructions with overlapping encodings that are disambiguated by field comparisons

[Mihail Popa]

Hi Daniel.

Unfortunately this requires a custom decoder method.
Take a look at the ARM back-end. There are plenty such examples.

Mihai


On 13 May 2014 12:47, Daniel Sanders <Daniel.Sanders at imgtec.com> wrote:

>  Hi,
>
>
>
> I'm not sure how to handle some of the trickier instruction encodings in
> MIPS64r6. My problem is that some instructions determine the operation
> based on the relationship between two fields. For example, 'beqc $rs, $rt,
> offset' (branch if equal, no delay slot) and bovc (branch if addition would
> overflow, no delay slot) share the same major opcode and field layout. When
> the register number $rs is less than the register number $rt, it is a beqc
> instruction. When the register number $rs is greater or equal to the
> register number $rt, it is a bovc.
>
>
>
> Unsurprisingly, defining both of these instructions in tablegen causes
> decoding conflicts. Are there any targets with similar encoding/decoding
> issues that I could look at?
>
>
>
> *Daniel Sanders*
>
> Leading Software Design Engineer, MIPS Processor IP
>
> Imagination Technologies Limited
>
> www.imgtec.com
>
>
>
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>
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