[LLVMdev] Replacing Platform Specific IR Codes with Generic Implementation and Introducing Macro Facilities

[Andrew Trick]

On May 10, 2014, at 7:47 AM, David Chisnall <David.Chisnall at cl.cam.ac.uk> wrote:

> On 10 May 2014, at 13:53, Tim Northover <t.p.northover at gmail.com> wrote:
> 
>> It doesn't make sense for everything though, particularly if you want
>> target-specific IR to simply not exist. What would you map ARM's
>> "ldrex" to on x86? 
> 
> This isn't a great example.  Having load-linked / store-conditional in the IR would make a number of transforms related to atomics easier.  We currently can't correctly model the weak compare-and-exchange from the C[++]11 memory model and we generate terrible code for a number of common atomic idioms on non-x86 platforms as a result.  

The IR is missing a weak variant of cmpxchg. But is there anything else missing at IR level? My understanding was that LLVM’s atomic memory ordering constraints are complete, but that codegen is not highly optimized, and maybe conservative for some targets. Which idiom do you have trouble with on non-x86?

-Andy