[LLVMdev] [RFC] Add compiler scheduling barriers

[Matt Arsenault]

On Jun 19, 2014, at 9:35 AM, Yi Kong <kongy.dev at gmail.com> wrote:

> Hi all,
> 
> I'm currently working on implementing ACLE extensions for ARM. There
> are some memory barrier intrinsics, i.e.__dsb and __isb that require
> the compiler not to reorder instructions around their corresponding
> built-in intrinsics(__builtin_arm_dsb, __builtin_arm_isb), including
> non-memory-access instructions.[1] This is currently not possible.
> 
> It is sometimes useful to prevent the compiler from reordering
> memory-access instructions as well. The only way to do that in both
> GCC and LLVM is using a in-line assembly hack:
>  asm volatile("" ::: "memory")
> 
> I propose adding two compiler scheduling barriers intrinsics to LLVM:
> __schedule_barrier_memory and __schedule_barrier_full. The former only
> prevents memory-access instructions reordering around the instruction
> and the latter stops all. So that __isb, for example, can be
> implemented something like:
>  inline void __isb() {
>    __schedule_barrier_full();
>    __builtin_arm_isb();
>    __schedule_barrier_full();
>  }
> 
> To implement these intrinsics, I think the best method is to add
> target-independent pseudo-instructions with appropriate
> properties(hasSideEffects for memory barrier and isTerminator for full
> barrier) and a pseudo-instruction elimination pass after the
> scheduling pass.
> 
> What do people think of this idea?
> 
> Cheers,
> 
> Yi

This sounds similar to the problem I want to solve with the nomemfence attribute http://lists.cs.uiuc.edu/pipermail/llvmdev/2014-January/069129.html

I had this about half implemented in December but I haven’t gotten back to finishing it yet

-Matt