[LLVMdev] Regarding Instruction definition in LLVM backend

[Arsen Hakobyan]

Hi all, 

My question is related to the register usage in instruction definition at
TARGETInstrInfo.td file.

I have defined new Target with it Registers and instructions.

Now I need to generate an instruction like:
  mov  MYREG1_NAME, MYREG2_NAME

for the built-in function taking one constant integer argument, such as
"__builtin_my_function_name(88)"

I wondering whether it is possible to do this using only TableGen ?

I assume that I should only define a class in TARGETInstrInfo.td file.

Currently I have done the following:

in TARGETRegisterInfo.td file I have defined the registers: MYREG1_NAME and
MYREG2_NAME
in TARGETInstrInfo.td file I have the following definitions:
def simm16      : Operand<i16> {
  let DecoderMethod= "DecodeSimm16";
  let OperandType = "OPERAND_IMMEDIATE";
}
class SII<bits<6> op, string instr_asm, Operand Imm> : 
         FI<op, (outs), (ins Imm:$val), !strconcat(instr_asm,
"\t$val"), [], IIAlu> {
    let rs = 0;
    let rt = 0;
}

def MOV : SII<0x21, "mov", simm16>;

def : TARGETPat<(int_my_builtin_function_name (imm:$val)), (MOV imm:$val)>;


I just found that the base Instruction class has Defs and Uses lists where
it is possible to pass the Registers, but actually I could not use them for
my situation.
I think that I should have Registers in a class "SII", for example like:

class SII<bits<6> op, string instr_asm, list<Register> Regs, Operand Imm>
: 
         FI<op, (outs), (ins Imm:$val), !strconcat(instr_asm,
"\t$Regs->0, $Regs->1"), [], IIAlu> {   /// I am not sure that I got
list elements correctly.
    let rs = 0;
    let rt = 0;
}

def MOV : SII<0x21, "mov", [MYREG1_NAME, MYREG2_NAME], simm16>;

but in this case there is a problem with pattern matching. 

I hope to find any good ideas/advices here.

Thanks for your time,
Arsen




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