[LLVMdev] [llvm] r210424 - Revert "Do materialize for floating point"

[Reed Kotler]

Why are you reverting patches for any area that you have no 
authorization for ?

No build was broken. This patch is fine.

I am authorized to check in to the Mips area and Daniel is the 
maintainer for that area.


On 06/08/2014 02:13 AM, Alp Toker wrote:
> Author: alp
> Date: Sun Jun  8 04:13:42 2014
> New Revision: 210424
>
> URL: http://llvm.org/viewvc/llvm-project?rev=210424&view=rev
> Log:
> Revert "Do materialize for floating point"
>
> 1) The commit was made despite profound lack of understanding:
>
>     "I did not understand the comment about using dyn_cast instead of isa. I will
>     commit as is and make the update after. You can explain what you meant to me."
>
>     Commit first, understand later isn't OK.
>
> 2) Review comments were simply ignored:
>
>     "Can you edit the summary to describe what the patch is for? It appears to be
>     a list of commits at the moment."
>
> 3) The patch got LGTM'd off-list without any indication of readiness.
>
> 4) The public mailing list was excluded from patch review so all of this was
>     hidden from the community.
>
> This reverts commit r210414.
>
> Removed:
>      llvm/trunk/test/CodeGen/Mips/Fast-ISel/simplestorefp1.ll
> Modified:
>      llvm/trunk/lib/Target/Mips/MipsFastISel.cpp
>
> Modified: llvm/trunk/lib/Target/Mips/MipsFastISel.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsFastISel.cpp?rev=210424&r1=210423&r2=210424&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Mips/MipsFastISel.cpp (original)
> +++ llvm/trunk/lib/Target/Mips/MipsFastISel.cpp Sun Jun  8 04:13:42 2014
> @@ -167,14 +167,9 @@ bool MipsFastISel::EmitStore(MVT VT, uns
>     //
>     // more cases will be handled here in following patches.
>     //
> -  if (VT == MVT::i32)
> -    EmitInstStore(Mips::SW, SrcReg, Addr.Base.Reg, Addr.Offset);
> -  else if (VT == MVT::f32)
> -    EmitInstStore(Mips::SWC1, SrcReg, Addr.Base.Reg, Addr.Offset);
> -  else if (VT == MVT::f64)
> -    EmitInstStore(Mips::SDC1, SrcReg, Addr.Base.Reg, Addr.Offset);
> -  else
> +  if (VT != MVT::i32)
>       return false;
> +  EmitInstStore(Mips::SW, SrcReg, Addr.Base.Reg, Addr.Offset);
>     return true;
>   }
>
> @@ -234,22 +229,6 @@ bool MipsFastISel::TargetSelectInstructi
>   }
>
>   unsigned MipsFastISel::MaterializeFP(const ConstantFP *CFP, MVT VT) {
> -  int64_t Imm = CFP->getValueAPF().bitcastToAPInt().getZExtValue();
> -  if (VT == MVT::f32) {
> -    const TargetRegisterClass *RC = &Mips::FGR32RegClass;
> -    unsigned DestReg = createResultReg(RC);
> -    unsigned TempReg = Materialize32BitInt(Imm, &Mips::GPR32RegClass);
> -    EmitInst(Mips::MTC1, DestReg).addReg(TempReg);
> -    return DestReg;
> -  } else if (VT == MVT::f64) {
> -    const TargetRegisterClass *RC = &Mips::AFGR64RegClass;
> -    unsigned DestReg = createResultReg(RC);
> -    unsigned TempReg1 = Materialize32BitInt(Imm >> 32, &Mips::GPR32RegClass);
> -    unsigned TempReg2 =
> -        Materialize32BitInt(Imm & 0xFFFFFFFF, &Mips::GPR32RegClass);
> -    EmitInst(Mips::BuildPairF64, DestReg).addReg(TempReg2).addReg(TempReg1);
> -    return DestReg;
> -  }
>     return 0;
>   }
>
>
> Removed: llvm/trunk/test/CodeGen/Mips/Fast-ISel/simplestorefp1.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/Fast-ISel/simplestorefp1.ll?rev=210423&view=auto
> ==============================================================================
> --- llvm/trunk/test/CodeGen/Mips/Fast-ISel/simplestorefp1.ll (original)
> +++ llvm/trunk/test/CodeGen/Mips/Fast-ISel/simplestorefp1.ll (removed)
> @@ -1,39 +0,0 @@
> -; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \
> -; RUN:     < %s | FileCheck %s
> -
> - at f = common global float 0.000000e+00, align 4
> - at de = common global double 0.000000e+00, align 8
> -
> -; Function Attrs: nounwind
> -define void @f1() #0 {
> -entry:
> -  store float 0x3FFA76C8C0000000, float* @f, align 4
> -  ret void
> -; CHECK:	.ent	f1
> -; CHECK:	lui	$[[REG1:[0-9]+]], 16339
> -; CHECK:	ori	$[[REG2:[0-9]+]], $[[REG1]], 46662
> -; CHECK:	mtc1	$[[REG2]], $f[[REG3:[0-9]+]]
> -; CHECK:	lw	$[[REG4:[0-9]+]], %got(f)(${{[0-9]+}})
> -; CHECK:	swc1	$f[[REG3]], 0($[[REG4]])
> -; CHECK: 	.end	f1
> -
> -}
> -
> -; Function Attrs: nounwind
> -define void @d1() #0 {
> -entry:
> -  store double 1.234567e+00, double* @de, align 8
> -; CHECK:	.ent	d1
> -; CHECK:	lui	$[[REG1a:[0-9]+]], 16371
> -; CHECK:	ori	$[[REG2a:[0-9]+]], $[[REG1a]], 49353
> -; CHECK:	lui	$[[REG1b:[0-9]+]], 21403
> -; CHECK:	ori	$[[REG2b:[0-9]+]], $[[REG1b]], 34951
> -; CHECK:	mtc1	$[[REG2b]], $f[[REG3b:[0-9]+]]
> -; CHECK:	mtc1	$[[REG2a]], $f[[REG3a:[0-9]+]]
> -; CHECK:	sdc1	$f[[REG3b]], 0(${{[0-9]+}})
> -; CHECK:	.end	d1
> -  ret void
> -}
> -
> -attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
> -
>