[LLVMdev] FPU cannot be compatible with -soft-float code on mips by llc

[Jim Grosbach]

Hi Robin,

It sounds like you want to support half (f16 in LLVM terms) as a storage only interchange format. AArch64 and X86 (among others) do the same thing. You shouldn’t need the “-soft-float” option or anything of that nature at all. That, as you’ve found, disables all hard float operations. There’s been some recent cleanup in how this is handled in LLVM that should help guide you in what the Mips backend needs to do. In particular, Tim Northover’s recent patch, r213374.

Regards,
  Jim

> On Jul 24, 2014, at 6:32 PM, 刘亚龙 <liuyalong.email at gmail.com> wrote:
> 
> Hi all,
>     -soft-float can not be rightly use by llc. All float function operation will call soft float, but not hard.
>     My mips device cannot support half float type, so I hack the llvm, and add soft half float and add -soft-float option.
>     I add the function define for __gnu_f2h_ieee() and __gnu_h2f_ieee (), and it can call the soft half float.
>     However, all the others function about float also call the soft float, how I do make only __gnu_f2h_ieee() use soft float, other use hard float???
> 
>     Thank you all !!
> 
> Cheers, 
>     Robin
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