[LLVMdev] setDesc vs MachineInstrBuilder

[Ryan Taylor]

Is there a way to assign multiple Register Classes to an instruction with
some priority or default? For example, have the default for an instruction
be Register Class A but also allow it to be valid for Register Class B (for
custom pass tuning)?

Thanks.


On Tue, Jul 15, 2014 at 7:32 PM, Ryan Taylor <ryta1203 at gmail.com> wrote:

> I would like to replace an instruction X that uses Y class register with
> the same functionality instruction Z (for example, Y, Z = add... of the
> same types) that uses W class register. I'm currently using a Machine
> Function Pass at the state MachineSSAOptimization (addPass(myPass) inside
> addMachineSSAOptimization() in MyTargetMachine.cpp. Inside my
> MachineFunctionPass I am changing the opcode via setDesc.
>
> I was hoping that I could just replace the instruction in this stage and
> the register allocator would pick up on the instruction and use the
> appropriate register class, but it is still producing Y class register
> instead of W?
>
> Should I be using MachineInstrBuilder instead of setDesc and if so why?
>
> Thanks.
>
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