[LLVMdev] Selection DAG node for 64-bit load

[Tom Stellard]

Hi

Do the two 32-bit bases need to be stored in consecutive registers?  If
so, you could still use the 64-bit loads and then use REQ_SEQUENCE to create
a pair of 32-bit registers.

-Tom

On Tue, Jul 08, 2014 at 01:46:30PM -0700, Iftekhar Chowdhury wrote:
> Yes, the target does not have 64-bit GPRs. But it still needs to support
> 64-bit address space.
> 
> Cheers,
> Iftekhar
> 
> 
> On Tue, Jul 8, 2014 at 1:19 PM, Hal Finkel <hfinkel at anl.gov> wrote:
> 
> > ----- Original Message -----
> > > From: "Iftekhar Chowdhury" <iftekhar.hc at gmail.com>
> > > To: llvmdev at cs.uiuc.edu
> > > Sent: Tuesday, July 8, 2014 1:06:44 PM
> > > Subject: [LLVMdev] Selection DAG node for 64-bit load
> > >
> > >
> > >
> > >
> > >
> > > Hi Fellow LLVM Experts,
> > >
> > > Currently, Selection DAG node for load seems to expect a 32-bit base
> > > and an offset. Is it possible to extend load node definition to 2
> > > 32-bit bases and an offset? Two 32-bit bases are supposed to
> > > represent one 64-bit address.
> > >
> > >
> >
> > I don't understand why you're suggesting this? Does your target have a
> > 64-bit address space but no 64-bit GPRs?
> >
> >  -Hal
> >
> > >
> > > Any suggestions, comments are much appreciated.
> > >
> > >
> > >
> > > Regards,
> > >
> > > Iftekhar
> > > _______________________________________________
> > > LLVM Developers mailing list
> > > LLVMdev at cs.uiuc.edu         http://llvm.cs.uiuc.edu
> > > http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev
> > >
> >
> > --
> > Hal Finkel
> > Assistant Computational Scientist
> > Leadership Computing Facility
> > Argonne National Laboratory
> >

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