[LLVMdev] Instructions on a target with no general purpose registers

[Steve Montgomery]

Hi Edwin,

as David says, I've implemented a back-end for the Freescale 8 and 16-bit microcontrollers, HC08, HC12, HCS12, S12, S12X, ... It's far from perfect and I've not finished but, as indicated in my off-list e-mail to you, I'd be happy to share tips and tricks.

I didn't have a particular problem with the small number of registers. I wrote instruction patterns in which the operand register classes often contained a single register. I found the default greedy register allocator handled this pretty well provided you remember to allow register classes to be inflated (implement MOS6502RegisterInfo::getLargestLegalSuperClass). If you don't them the register allocator has to reload into the same class that a vreg was spilled from which means it can't break circular dependencies sometimes. If a dependency can't be broken then the allocator will report running out of registers.

If you go this route, you will also need to implement MOS6502InstrInfo::foldMemoryOperandImpl so you can fold the reloads into other instructions.

LLVM assumes that each binary operation has a corresponding instruction that can operate on register operands. This isn't the case for the microcontrollers I've been working on and isn't the case for the 6502 either. I think the best solution is to implement pseudo instructions and let the register allocator's spill/reload deal with them. Much of the time, an operand will be reloaded, so can be folded. Any pseudos that remain after register allocation can be handled by spilling to memory, e.g. a dedicated fixed offset in the stack frame.

If you decide to use zero-page as registers, and not tell LLVM about A, X and Y, then you've got more registers and they can all be the same register class. I imagine it might be best in this situation to lower the IR mainly to library calls.

Hope that helps. Let me know if you want any further info about how I implemented the CPU12 backend.

Regards,

Steve

On 5 Jul 2014, at 19:07, David Chisnall <David.Chisnall at cl.cam.ac.uk> wrote:

> Hi Edwin,
> 
> I'm not sure how actively he follows the lists, but you should talk to Steve Montgomery.  He has some experience in porting LLVM to 8-bit microcontrollers (and gave a talk about it at the Cambridge LLVM Day in 2012).
> 
> David
> 
> 
> On 5 Jul 2014, at 14:59, Edwin Amsler <edwinguy at gmail.com> wrote:
> 
>> I've mentioned my sneaky plans to target the MOS6502 here before.
>> 
>> The big issue I think is that a lot of instructions don't really have a choice for output register. It all just goes into the accumulator, X index, or Y index based on the specific instruction.
>> 
>> So, my question is, when I'm defining my ins, outs and registers for these instructions, is it going to be a problem that different instructions outputs are defined by the function that is called? And I guess, how do I tell LLVM it can't pick any old register for a given instruction?
>> 
>> Thanks,
>> 
>> Edwin
>> _______________________________________________
>> LLVM Developers mailing list
>> LLVMdev at cs.uiuc.edu         http://llvm.cs.uiuc.edu
>> http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev
> 
> 
> _______________________________________________
> LLVM Developers mailing list
> LLVMdev at cs.uiuc.edu         http://llvm.cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev