[LLVMdev] Load Instruction that changes value of two registers

[Quentin Colombet]

Hi Markus,

On Jan 28, 2014, at 3:30 PM, Markus Timpl <tima0900 at googlemail.com> wrote:

> Hello,
> I'm writing a backend for an architecture that only has LOAD Instructions that first copy the old value of the target register in another register and after that load the provided value into the register.
If I understand correctly, your load performs in parallel a copy and a load:
loadedVal<dstReg> load addr || <someReg> copy <dstReg> 

If you forget about the copy part, you can simply model your load like this:
<dstReg>, <someReg> load addr

<someReg> will be an implicit definition and your good to go.
Obviously, this is not optimal.

Note that, the original code (dot = load addr) does not define <someReg>, so I guess you have some rules to assign it (like <sameReg> = <dstReg> + 1).
Therefore you may have to create a specific register class for that:
<BigDstReg> load addr
<dstReg> = BigDstReg.subIdx
And have a pattern using a EXTRACT_SUBREG (see ARM NEON).


Now, if you want to remember that <someReg> is not some trash value but contains the value of <dstReg> before this instruction, this is a different story.

The tricky part here is how do you tell the compiler where does dstReg come from? Indeed, you will know that, only when you will choose it.
You could make this choice a priori, but this is not optimal either.
Anyhow, I do not think there is a straight answer for your case.

Note: I was assuming that reg2 depends on the choice of reg1, if it is not the case, then, this is slightly a different story.

-Quentin


>  
> Example of an addition:
> load a, reg1; // -> copies old value of reg1 in reg2 and loads value from a into reg1
> load b, reg1; // -> copies old value of reg1 in reg2 and loads value from b into reg1
> add reg1, reg2; // adds values from a and b and saves the result into reg1
>  
> So I need to describe the "load X, reg1" Instruction so that LLVM understands it correctly.
> How can I do that in LLVM? Where is the best place to do that(TableGen, Instruction Selection, Instruction Lowering)?
>  
> It would be fine if I could tell LLVM that reg2 is invalid after a load Operation, but I don#t know how to do that...
> I tried the following in TableGen to let LLVM know that Resg2 isn't valid anymore after a load but it didn't produce the desired result:
>  
> let Defs = [Regs2] in
> {
> def LD: Inst<(outs Regs1:$dst), (ins MEM:$addr),
> 
> "load $addr, $dst;",
> 
> [(set Regs1:$dst, (load addr:$addr))]>;
> 
> }
> 
>  
> Thanks in advance,
> Markus
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