[LLVMdev] New machine model questions

[Andrew Trick]

On Jan 28, 2014, at 9:22 AM, Daniel Sanders <Daniel.Sanders at imgtec.com> wrote:

> llvm-tblgen -I /s/fix/lib/Target/ARM -I /s/fix/include -I  /s/fix/include -I /s/fix/lib/Target -gen-subtarget -o  ARMGenSubtargetInfo.inc /s/fix/lib/Target/ARM/ARM.td -debug-only=subtarget-emitter
>  
> It will list all instructions and print "No machine model for <subtarget>"
> You will also get an assert in the scheduler, unless you add the following flag to your mode:
>  
>   let CompleteModel = 0;
>  
> That's perfect, thanks.


FYI

Someone just pointed out that when the instruction has an itinerary class, and the machine model has no ItinRW, you get a warning that the machine model is missing for the instruction, even if the instruction has a SchedRW list. (I really didn’t want to support this situation, but may end up fixing the warning anyway for x86).

I don’t think you’ll run into it since you’re not putting SchedRW lists on the instruction definitions themselves.

-Andy
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