[LLVMdev] basic block missing after MachineInstr packetizing

[Sergei Larin]

Andy is right. There are different ways to “set” a bundle.

 

Why it does not happen to Hexagon – my guess would be that it could have been fixed locally, but has not been up streamed yet.

 

> I am not sure dependency dag is correct when it gets scheduled and packetized

 

Without this, you cannot really expect scheduler or packetizer to do the right “thing”. Majority of problems I see in this code is from improper dependency information, so I suggest you try to figure this out first. If your local workaround would uncover some bigger issue, please update the bugzilla ticket.

 

Hope this somewhat helpful… 

 

Sergei

 

---

Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation

 

From: Andrew Trick [mailto:atrick at apple.com] 
Sent: Thursday, January 09, 2014 4:16 PM
To: 杨勇勇
Cc: Sergei Larin; "LLVM-Dev ‎[llvmdev at cs.uiuc.edu]‎"
Subject: Re: [LLVMdev] basic block missing after MachineInstr packetizing

 

 

On Jan 8, 2014, at 6:12 PM, 杨勇勇 <triple.yang at gmail.com> wrote:





Sergei, Thank you for your attention.

 

My target is a custom VLIW DSP. I am not sure dependency dag is correct when it gets scheduled and packetized. Months ago, I submitted a bug at http://llvm.org/bugs/show_bug.cgi?id=17894 which explained more details.

 

I am not sure my understanding of this bug is proper, but modified my local codes this way and it works for my target when scheduling and packetizing.

 

Well why this problem does not occur for Hexagon target?

 

FYI: if there is a bug in finalizeBundle() one possible fix is not calling it. Nothing in the MachineIR requires finalizeBundle to be called, bundles are perfectly valid without it. It is only there for legacy reasons because some targets want to see the extra BUNDLE marker with duplicate MachineOperands.

 

-Andy





 

Regards.

 

2014/1/9 Sergei Larin <slarin at codeaurora.org>

Yang,

 

  There is not enough info here to understand what is going wrong – what is your target? Is dependency dag correct going into scheduling and packetization?

 

Sergei

 

---

Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation

 

From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of ???
Sent: Sunday, November 10, 2013 8:31 PM
To: LLVM-Dev ‎[llvmdev at cs.uiuc.edu]‎
Subject: [LLVMdev] basic block missing after MachineInstr packetizing

 

Hi, all,

 

When I schedule machine instructions in a VLIW way and packetize them, a problem is encountered, and I will show it use a simplified case as follows.

 

############ original instruction sequence

...

insn1

...

jump  LBB0_xx

...

LBB0_xx:

...

 

############ expected instruction sequence after scheduling and packetizing

insn1; jump LBB0_xx


...

LBB0_xx:

...

 

############ generated instruction sequence

insn1; jump LBB0_xx


...

#BB#xx:

...

 

BasicBlock BB#xx is commented out when insn1 and "jump LBB0_xx" is bundled.

I guess the reference to LBB0_xx is deconstructed when insn1 and LBB0_xx are packetized together thus BB#xx is commented out.

 

What should we do if the reference to LBB0_xx has to be maintained?

 

Thanks ahead!


--

杨勇勇 (Yang Yong-Yong)





 

-- 
杨勇勇 (Yang Yong-Yong)

_______________________________________________
LLVM Developers mailing list
LLVMdev at cs.uiuc.edu         http://llvm.cs.uiuc.edu <http://llvm.cs.uiuc.edu/> 
http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev

 

-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20140110/772b108e/attachment.html>